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HT82A834R usb audio mcu rev. 1.00 1 august 27, 2007 general description the HT82A834R is an 8-bit high performance risc-like microcontroller designed for usb phone product applications. the HT82A834R combines a 16-bit pcm adc, usb transceiver, sie (serial interface engine), audio class processing unit, fifo and an 8-bit mcu into a single chip. the dac in the HT82A834R operates at a sampling rate of 48khz/8khz and the 16-bit pcm adc operates at 8/16khz for the microphone input. for the dac, the HT82A834R has a digital programmable gain amplifier. the gain range is from -32db to +6db. for the adc input, the digital gain range is from 0db to 19.5db. features operating voltage: f sys = 6m/12mhz: 3.3v~5.5v 24 bidirectional i/o lines (max.) two 16-bit programmable timer/event counters and overflow interrupts 4096 15 program memory rom 192 8 data memory ram (bank 0) usb 2.0 full speed compatible usb spec v1.1 full speed operation and usb audio device class spec v1.0 embedded high-performance 16 bit pcm adc built-in digital pga (programmable gain amplifier) 48khz/8khz sampling rate for audio playback controlled by software option 8khz/16khz audio recording sampling rate embedded class ab speaker driver power amplifier embedded high performance 16 bit audio dac supports audio playback digital volume control 5 endpoints supported (endpoint 0 included) supports 1 control, 2 interrupt, 2 isochronous transfer two hardware implemented isochronous transfers total fifo size: 496 bytes (8, 8, 384, 64, 32 for ep0~ep4) programmable frequency divider (pfd) integrated spi hardware circuit play/record interrupt halt and wake-up features reduce power consumption watchdog timer 16-level subroutine nesting bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions executed within one or two machine cycles low voltage reset function (3.0v 0.3v) 48-pin ssop/lqfp package
block diagram HT82A834R rev. 1.00 2 august 27, 2007

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pin assignment pin description pin name i/o description pa0~pa7 i/o bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input with or without a pull-high resistor (by configuration option). avdd2 audio power amplifier positive power supply rout o right driver analog output lout o left driver analog output avss2 audio power amplifier negative power supply, ground avss1 audio dac negative power supply, ground bias a capacitor should be connected to ground to increase half-supply stability music_in i power amplifier signal source if register bit selw = 1 . the analog signal input will amplify by the power amp then output to rout and lout at the same time. avdd1 audio dac positive power supply avdd3 adc positive power supply vagref o adc analog ground reference voltage (should left open or connect a bypass capacitor (ex:100 pf) to ground) vag o adc analog ground voltage (should connect a bypass capacitor (ex:1 uf) to ground) ti+ i op amp non-inverting input ti- i op amp inverting input tg o op amp gain setting output HT82A834R rev. 1.00 3 august 27, 2007

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pin name i/o description avss3 adc negative power supply, ground pb7~pb0 i/o bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options, bit option). dvss2 negative digital & i/o power supply, ground pc7/sck i/o can be software optioned as a bidirectional input/output or serial interface clock signal. pc6/scs i/o can be software optioned as a bidirectional input/output or serial interface slave select signal. pc5/sdi i/o or i can be software optioned as a bidirectional input/output or serial data input. pc4/sdo i/o or o can be software optioned as a bidirectional input/output or serial data output. pc3 i/o bidirectional i/o lines. software instructions determine if the pin is a cmos output or schmitt trigger input with pull-high resistor (determined by configuration option). pc2/tmr1, pc1/tmr0 i/o software instructions determine if the pin is a cmos output or schmitt trigger input with pull-high resistor. tmr0, tmr1 are pin shared with pc1, pc2 respectively pc0/bz i/o or o can be software optioned as a bidirectional input/output or as a pfd output. osci osco i o osci, osco are connected to an 6mhz or 12mhz crystal/resonator (determined by software instructions) for the internal system clock reset i schmitt trigger reset input, active low dvdd1 positive digital power supply usbdn i/o usbd- line. the usb function is controlled by a software control register usbdp i/o usbd+ line. the usb function is controlled by a software control register v33o o 3.3v regulator output dvss1 negative digital power supply, ground absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT82A834R rev. 1.00 4 august 27, 2007
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 5v 3.3 5.0 5.5 v i dd operating current 5v no load, f sys =12mhz, adc on, dac on 12 ma 5v no load, f sys =12mhz, adc off, dac off 8 ma i sus suspend current 5v no load, system halt, usb transceiver and 3.3v regulator on 330 a v il1 input low voltage for i/o ports 5v 0 0.3v dd v v ih1 input high voltage for i/o ports 5v 0.7v dd v dd v v il2 input low voltage (reset )5v 0 0.4v dd v v ih2 input high voltage (reset )5v 0.9v dd v dd v i ol i/o port sink current 5v v ol =0.1v dd 5 ma i oh i/o port source current 5v v oh =0.7v dd 5 ma r ph pull-high resistance 5v 30 40 80 k v lvr low voltage reset 5v 2.7 3.0 3.3 v v v33o 3.3v regulator output 5v i v33o = 5ma 3.0 3.3 3.6 v dac+power amp: test condition: measurement bandwidth 20hz to 20khz, f s = 48khz. line output series capacitor with 220 f. thd+n thd+n note1 5v 4 load 30 db 8 load 35 snr da signal to noise ratio note1 5v 4 load 81 db 8 load 82 dr dynamic range 5v 4 load 87 db 8 load 88 p out output power 5v 4 load, thd=10% 400 mw/ch 8 load, thd=10% 200 pcm adc snr ad signal to noise ratio 5v 77 db vag reference voltage 5v 2 v v peak peak single frequency tone amplitude without clipping 5v 1.575 v pk note.1: sine wave input at 1khz, 6db a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 0.4 12 mhz t wdtosc watchdog oscillator period 5v 100 s t res reset input pulse width 1 s t sst system start-up timer period 1024 t sys t int interrupt pulse width 1 s note: t sys =1/f sys HT82A834R rev. 1.00 5 august 27, 2007
HT82A834R rev. 1.00 6 august 27, 2007 functional description execution flow the system clock for the microcontroller is sourced from a crystal oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to be effectively executed in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading to the pcl register, performing a sub - routine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from inter - rupts, the pc manipulates the program transfer by load - ing the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be 1 3 0 1 3 0 1 3 0 . " % % 4 6 ' a % % 4 9 6 . " % % 4 > 6 ' a % % 4 6 . " % % 4 > 1 6 ' a % % 4 > 6 > > 1 % &
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& 6 execution flow mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 usb interrupt 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 play interrupt 000000010000 serial interface interrupt 000000010100 record interrupt 000000011000 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits
HT82A834R rev. 1.00 7 august 27, 2007 within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. program memory prom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 4096 15 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after a chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in- terrupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch this area is reserved for the timer/event counter 1 in- terrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00ch. location 010h this area is reserved for the play interrupt service pro - gram. if play data is valid, and the interrupt is enabled and the stack is not full, the program begins execution at location 010h. location 014h this area is reserved for when 8 bits of data have been received or transmitted successfully from the se - rial interface. if the related interrupts are enabled, and the stack is not full, the program begins execution at location 014h. location 018h this area is reserved for the record interrupt service program. if the record data valid, the interrupt is en - abled and the stack is not full, the program begins ex - ecution at location 018h. table location any location in the program memory can be used as a look-up table. there are three methods to read the rom data using two table read instructions: tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows:
the instruction tabrdc [m] (the current page, one page=256 words), where the table location is defined by tblp (07h) in the current page. the configuration option, tbhp, is disabled (default).
the instruction tabrdc [m] , where the table lo - cation is defined by registers tblp (07h) and tbhp (01fh). the configuration option, tbhp, is enabled.
the instruction tabrdl [m] , where the table lo - cations is defined by register tblp (07h) in the last page (0f00h~0fffh). , % % :
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% program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits when tbhp is disabled p11~p8: current program counter bits @7~@0: table pointer bits tbhp register bit3~bit0 when tbhp is enabled
HT82A834R rev. 1.00 8 august 27, 2007 only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the remaining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the table pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before accessing the table, the location must be placed in the tblp and tbhp registers. (if the configuration option tbhp is disabled, the value in tbhp has no effect). tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine is likely to be changed by the table read instruction used in the isr. as a result errors may occur. in other words, using the table read instruction in the main routine and in the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the requirements. once the tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by the tblp and tbhp register value. otherwise, if the configuration option tbhp is disabled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the stack pointer will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 16 return ad - dresses are stored). data memory ram the data memory is divided into two functional groups: namely; special function registers and general purpose data memory, bank 0: 192 8 bits. most are read/write, but some are read only. the special function registers include the indirect addressing registers (r0;00h, r1;02h), bank register (bp;04h), timer/event counter 0 higher order byte register (tmr0h;0ch), timer/event counter 0 lower order byte register (tmr0l;0dh), timer/event counter 0 control register (tmr0c;0eh), timer/event counter 1 higher order byte register (tmr1h;0fh), timer/event counter 1 lower order byte register (tmr1l;10h), timer/event counter 1 control register (tmr1c;11h), program counter lower-order byte register (pcl;06h), memory pointer registers (mp0;01h, mp1;03h), accumulator (acc;05h), table pointer (tblp;07h, tbhp;1fh), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register0 (intc0;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h), i/o control registers (pac;13h, pbc;15h, pcc;17h). digital volume control register (usvc;1ch). usb status and control register (usc;20h), usb endpoint interrupt status register (usr;21h), system clock control register (ucc;22h). address and remote wakeup register (awr;23h), stall register (24h), sies register (25h), misc register (26h), setio register (27h). fifo0~fifo4 register (28h~2ch). dac_limit_l register (2dh), dac_limit_h register (2eh), dac_wr register (2fh). pga_ctrl register (30h). pfd control register (pfdc;31h). pfd data register (pfdd;32h). mode_ctrl register (34h). serial bus control register (sbcr;35h), serial bus data register (sbdr;36h). play data left channel (play_datal_l;3ah, play_datal_h;3bh), play data right channel (play_datar_l;3ch, play_ datar_h;3dh). record data (record_data_l; 3eh, record_data_h; 3fh). the remaining space before the 40h is reserved for future expanded usage, reading these locations will return a result of 00h . the general purpose data memory, addressed from 40h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1).
HT82A834R rev. 1.00 9 august 27, 2007 indirect addressing register locations 00h and 02h are indirect addressing regis - ters that are not physically implemented. any read/write operation on [00h] ([02h]) will access the data memory pointed to by mp0 (mp1). reading location 00h (02h) indirectly will return the result 00h. writing indirectly re - sults in no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers (mp0 and mp1) are 8-bit registers used to ac - cess the ram by combining corresponding indirect ad - dressing registers. bank pointer the bank pointer is used to assign the accessed ram bank. when the users want to access the ram bank 0, a 0 should be loaded onto bp. ram locations before 40h in any bank are overlapped. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults from those intended. the to flag can be affected only by a system power-up, a wdt time-out or executing the clr wdt or halt instruction. the z, ov, ac and c flags generally reflect the status of the latest operations. , b % ) % & % $ & %
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HT82A834R rev. 1.00 10 august 27, 2007 in addition, upon entering the interrupt sequence or exe - cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides a usb interrupt, internal timer/event counter interrupts, play/record data valid interrupt and a serial interface interrupt. the interrupt control register0 (intc0;0bh) and interrupt control register1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or intc1 may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. the usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of the intc0) will be set. accessing the corresponding usb fifo from the pc the usb suspend signal from the pc the usb resume signal from the pc usb reset signal when the interrupt is enabled, the stack is not full and the usb interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (usbf) and emi bits will be cleared to disable other interrupts. when the pc host accesses the fifo of the HT82A834R, the corresponding request bit of the usr is set, and a usb interrupt is triggered. so the user can easily determine which fifo has been accessed. when the interrupt has been served, the corresponding bit should be cleared by firmware. when the HT82A834R receives a usb suspend signal from the host pc, the suspend line (bit0 of usc) of the HT82A834R is set and a usb interrupt is also triggered. also when the HT82A834R receives a resume signal from the host pc, the resume line (bit3 of usc) of the HT82A834R is set and a usb interrupt is triggered. the internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (bit 5 of intc0), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the internal timer/event counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (bit 6 of intc0), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and t1f is set, a subroutine call to location 0ch will occur. the bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register
HT82A834R rev. 1.00 11 august 27, 2007 related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. the play interrupt is initialized by setting the play interrupt request flag (bit 4 of intc1), caused by a play data valid. when the interrupt is enabled, the stack is not full and the playf is set, a subroutine call to location 10h will occur. the related interrupt request flag (playf) will be reset and the emi bit cleared to disable further interrupts. if play_mode (bit 3 of mode_ctrl register) is set to 1 , the play interrupt frequency will change to 8khz, otherwise the interrupt frequency is 48khz. the serial interface interrupt is indicated by the interrupt flag (sif; bit 5 of intc1), that is generated by the reception or transfer of a complete 8-bits of data between the HT82A834R and the external device. the serial interface interrupt is controlled by setting the serial interface interrupt control bit (esii; bit 1 of intc1). after the interrupt is enabled (by setting sben; bit 4 of sbcr), and the stack is not full and the sif is set, a subroutine call to location 14h occurs. the record interrupt is initialized by setting the record interrupt request flag (bit 6 of intc1), caused by a record data valid. when the interrupt is enabled, the stack is not full and recf is set, a subroutine call to location 18h will occur. the related interrupt request flag (recf) will be reset and the emi bit cleared to disable further interrupts. if adc powered down (ad_enb =1) or usb clock disabled (usbcken=0), the record interrupt will be disabled. during the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the reti instruction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector usb interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch play interrupt 4 10h serial interface interrupt 5 14h record interrupt 6 18h it is recommended that a program does not use the call subroutine within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the call operates in the interrupt subroutine. bit no. label function 0 emi controls the master (global) interrupt (1=enable; 0=disable) 1 eui controls the usb interrupt (1=enable; 0=disable) 2 et0i controls the timer/event counter 0 interrupt (1=enable; 0=disable) 3 et1i controls the timer/event counter 1 interrupt (1=enable; 0=disable) 4 usbf usb interrupt request flag (1=active; 0=inactive) 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc0 (0bh) register bit no. label function 0 eplayi play interrupt (1=enable; 0=disable) 1 esii control serial interface interrupt (1=enable; 0=disable) 2 reci record interrupt (1=enable; 0=disable) 3, 7 unused bit, read as 0 4 playf play interrupt request flag (1=active; 0=inactive) 5 sif serial interface interrupt request flag (1=active; 0=inactive) 6 recf record interrupt request flag (1=active; 0=inactive) intc1 (1eh) register
HT82A834R rev. 1.00 12 august 27, 2007 oscillator configuration the microcontroller contains an integrated oscillator cir - cuit. this oscillator is designed for the system clock. the halt mode stops the system oscillator and ignores any external signals to conserve power. a crystal across osci and osco is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. if preferred, a resonator can also be connected between osci and osco for oscillation to occur, but two external capacitors connected between osci, osco and ground are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock stops running, but the wdt oscillator still continues to run. the wdt oscillator can be disabled by a configuration option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or the instruction clock (system clock/4). the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the wdt can be disabled by a configuration option. however, if the wdt is disabled, all executions related to the wdt lead to no operation. when the wdt clock source is selected, it will be first divided by 256 (8-stage) to get the nominal time-out period. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 can give different time-out periods. the wdt osc period is typically 65 s. this time-out period may vary with temperature, vdd and process variations. the wdt osc always keeps running in any operation mode. if the instruction clock is selected as the wdt clock source, the wdt operates in the same manner except in the halt mode. in the halt mode, the wdt stops counting and lose its protecting purpose. in this situation the logic can only be re-started by external logic. the high nibble of the wdts is reserved for the dac write mode. the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the halt mode, the overflow initializes a warm reset , and only the program counter and stack pointer are reset to zero. to clear the contents of the wdt, there are three meth- ods to be adopted, i.e., an external reset (a low level to reset ), a software instruction, and a halt instruc- tion. there are two types of software instructions; clr & % & &
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& % watchdog timer bit no. label function 0 1 2 ws0 ws1 ws2 watchdog timer division ratio selection bits bit 2,1,0 = 000, division ratio = 1:1 bit 2,1,0 = 001, division ratio = 1:2 bit 2,1,0 = 010, division ratio = 1:4 bit 2,1,0 = 011, division ratio = 1:8 bit 2,1,0 = 100, division ratio = 1:16 bit 2,1,0 = 101, division ratio = 1:32 bit 2,1,0 = 110, division ratio = 1:64 bit 2,1,0 = 111, division ratio = 1:128 3 unused bit, read as 0 7~4 t3~t0 test mode setting bits (t3,t2,t1,t0) = (0,1,0,1), enter dac write mode. otherwise normal operation. wdts (09h) register
HT82A834R rev. 1.00 13 august 27, 2007 wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option clr wdt times selection option. if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two instructions have to be executed to clear the wdt; otherwise, the wdt may reset the chip due to a time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following: the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on-chip ram and registers remain unchanged. the wdt and wdt prescaler will be cleared and re - counted again (if the wdt clock is from the wdt os - cillator). all of the i/o ports remain in their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig- nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per- forms a warm reset . after the to and pdf flags are examined, the cause for chip reset can be determined. the pdf flag is cleared by a system power-up or exe- cuting the clr wdt instruction and is set when exe- cuting the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; the others remain in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by configuration option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if it awakens from an interrupt, two se - quence may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the inter - rupt is enabled and the stack is not full, the regular inter - rupt response takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. the adc, dac and pa will all be powered down when in the halt mode. reset there are four ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation usb reset the time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and stack pointer, leaving the other circuits in their original state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condi - tion when the reset conditions are met. by examining the pdf and to flags, the program can distinguish be - tween different chip resets . to pdf reset conditions 0 0 reset reset during power-up u u reset reset during normal operation 0 1 reset wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys - tem resets (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack
HT82A834R rev. 1.00 14 august 27, 2007 the registers status are summarized in the following table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu 0000 0111 0000 0111 status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 usvc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usb_state 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 2 ' ' ) ) b ) b ) - . ) - ) . reset circuit % c !
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HT82A834R rev. 1.00 15 august 27, 2007 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu usc 1000 0000 uuxx uuuu 10xx 0000 10xx 0000 10xx uuuu 1000 0u00 1000 0u00 usr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 00uu 0000 00uu 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sies 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 setio xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo4 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 dac_limit_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dac_limit_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dac _wr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pga_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu 00uu uuuu pfdc 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 pfdd 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 mode_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 0uuu sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu record_in_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_in_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datal_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datal_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datar_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datar_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_data_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_data_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown - stands for undefined
HT82A834R rev. 1.00 16 august 27, 2007 timer/event counter two timer/event counters (tmr0, tmr1) are implemented in the microcontroller. the timer/event counter 0/1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are six registers related to the timer/event counter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). for 16-bit timer to write data to tmr0/1l will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr0/1h will transfer the specified data and the contents of the lower-order byte buffer to tmr0/1h and tmr0/1l registers. the timer/event counter 0/1 preload register is changed by each writing tmr0/1h operations. reading tmr0/1h will latch the contents of tmr0/1h and tmr0/1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr0/1l will read the contents of the lower-order byte buffer. the tmr0c (tmr1c) is the timer/event counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal clock source. finally, the pulse width measurement mode can be used to count the high level or low level duration of the external signal (tmr0, tmr1), and the counting is based on the internal clock source. in the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at ffffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (t0f; bit 5 of intc0, t1f; bit 6 of intc0). in the pulse width measurement mode with the values of the ton and te bits equal to 1, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the te bit is 0 ), it will start counting until the tmr0 (tmr1) returns to the original level and resets ton. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until ton is set. the cycle measurement will re-function as long as it receives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c or tmr1c) should be set to 1. in the pulse width measurement mode, ton is automatically cleared after the measurement cycle is completed. but in the other two modes, ton can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources. no matter what the operation mode is, writing a 0 to et0i or et1i disables the related interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. the timer/event counter still continues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors, as this may results in a counting error. blocking of the clock should be taken into account by the programmer. ) ) ( ' ) & % "
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HT82A834R rev. 1.00 17 august 27, 2007 bit no. label function 0~2, 5 unused bit, read as 0 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1=count on falling edge; 0=count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1=start counting on the rising edge, stop on the falling edge; 0=start counting on the falling edge, stop on the rising edge 4 ton enable/disable the timer counting (0=disable; 1=enable) 6 7 tm0 tm1 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh), tmr1c (11h) register input/output ports there are 24 bidirectional input/output lines in the micro-controller, labeled from pa to pc, which are mapped to the data memory of [12h], [14h], [16h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. to function as an input, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1 the input will read the pad state. if the control register bit is 0 the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos configurations can be selected. these control registers are mapped to locations 13h, 15h, 17h. after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high 2 ) * + , ) * , + ) ( , 7 ( ) 1 ( 3 0 ( ( 8 ( + (
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% 8 % #
% + input/output ports
HT82A834R rev. 1.00 18 august 27, 2007 options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h ) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. low voltage reset lvr (by configuration option) the lvr option is 3.0v. the microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) condition has to remain in its condition for a time exceeding 1ms. if the low voltage state does not exceed 1ms, the lvr will ig - nore it and will not perform a reset function. the lvr uses the or function with the external reset signal to perform a chip reset. suspend wake-up and remote wake-up if there is no signal on the usb bus for over 3ms, the HT82A834R will go into a suspend mode. the suspend line (bit 0 of the usc) will be set to 1 and a usb interrupt is triggered to indicate that the HT82A834R should jump to the suspend state to meet the requirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the firmware should disable the usb clock by clearing usbcken (bit3 of ucc) to 0 . also the user can further decrease the suspend current by setting susp2 (bit4 of the ucc). when the resume signal is sent out by the host, the HT82A834R will be woken up by the usb interrupt and the resume line (bit 3 of usc) will be set. in order to make the HT82A834R work properly, the firmware must set usbcken (bit 3 of ucc) to 1 and clear susp2 (bit4 of the ucc). since the resume signal will be cleared before the idle signal is sent out by the host and the suspend line (bit 0 of usc) will go to 0 . so when the mcu is detecting the suspend line (bit0 of usc), the condition of the resume line should be noted and taken into consideration. the following is the timing diagram: the device with remote wake up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of usc). once the usb host receives the wake-up signal from the HT82A834R, it will send a resume signal to the device. the timing is as follows: usb interface the HT82A834R device has 5 endpoints (ep0~ep4). ep0 supports control transfer. ep1 and ep4 support interrupt transfer. ep2 supports isochronous out transfer. ep3 supports isochronous in transfer. these registers, including usc (20h), usr (21h), ucc (22h), awr (23h), stall (24h), sies (25h), misc (26h), fifo0 (28h), fifo1 (29h), fifo2 (2ah), fifo3 (2bh), fifo4 (2ch) are used for the usb function. the fifo size of each fifo is 8 bytes (fifo0), 8 bytes (fifo1), 384 bytes (fifo2), 64 bytes (fifo3), 32 bytes (fifo4). the total is 496 bytes. urd (bit7 of usc) is the usb reset signal control function definition bit. ' , % % & , < ' , % % & , < - % 1 - - % , % !
HT82A834R rev. 1.00 19 august 27, 2007 bit no. label r/w reset functions 0 susp r 0 read only, usb suspend indication. when this bit is set to 1 (set by sie), it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high. 1 rmwk r/w 0 usb remote wake-up command. it is set by mcu to force the usb host to leave the suspend mode. 2 urst r/w 0 usb reset indication. this bit is set/cleared by the usb sie. this bit is used to detect a usb reset event on the usb bus. when this bit is set to 1 , this indicates that a usb reset has occurred and that a usb interrupt will be initialized. 3 resume r 0 usb resume indication. when the usb leaves the suspend mode, this bit is set to 1 (set by sie). when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set usbcken and clear susp2 (in the ucc register) to enable the sie detect function. resume will be cleared when the susp goes to 0 . when the mcu is detecting the susp, the condition of resume (causes the mcu to wake-up) should be noted and taken into consideration. 4 v33c r/w 0 0/1: turn-off/on v33o output 5 pllen r/w 0 0: turn on pll (default mode) 1: turn off pll 6 crcfg r/w 0 crc error condition failure flag. crcfg will be set by hardware and the crcfg need to be cleared by firmware. 7 urd r/w 1 usb reset signal control function definition 1: usb reset signal will reset mcu 0: usb reset signal cannot reset mcu usc (20h) register the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (usb). the endpoint request flags (ep0f, ep1f, ep2f, ep3f, ep4f) are used to indicate which end- points are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and the usb inter- rupt will occur (if the usb interrupt is enabled and the stack is not full). when the active endpoint request flag is serviced, the endpoint request flag has to be cleared to 0 by software. bit no. label r/w reset functions 0 ep0f r/w 0 when this bit is set to 1 (set by sie), it indicates that endpoint 0 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 1 ep1f r/w 0 when this bit is set to 1 (set by sie), it indicates that endpoint 1 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 2 ep2f r/w 0 when this bit is set to 1 (set by sie), it indicates that endpoint 2 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 3 ep3f r/w 0 when this bit is set to 1 (set by sie), it indicates that endpoint 3 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 4 ep4f r/w 0 when this bit is set to 1 (set by sie), it indicates that endpoint 4 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 5~7 undefined bit, read as 0 . usr (21h) register
HT82A834R rev. 1.00 20 august 27, 2007 there is a system clock control register implemented to select the clock used in the mcu. this register consists of a usb clock control bit (usbcken), a second suspend mode control bit (susp2) and a system clock selection bit (sysclk). the endpoint selection is determined by eps2, eps1 and eps0. bit no. label r/w reset functions 0~2 eps0~ eps2 r/w 0 accessing endpoint fifo selection, eps2, eps1, eps0: 000: select endpoint 0 fifo 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: select endpoint 4 fifo 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used if the selected endpoints do not exist, the related function will be absent. 3 usbcken r/w 0 usb clock control bit. when this bit is set to 1 , it indicates that the usb clock is enabled. otherwise, the usb clock is turned-off. 4 susp2 r/w 0 this bit is used for reducing power consumption in the suspend mode. in normal mode, clear this bit to 0 in the halt mode, set this bit to 1 to reducing power consumption. 5 f sys 16mhz r/w 0 this bit is used to define if the mcu system clock comes from an external osc or comes from the pll output 16mhz clock. 0: system clock sourced from osc 1: system clock sourced from the pll output 16mhz 6 sysclk r/w 0 this bit is used to specify the mcu system clock oscillator frequency. for a 6mhz crystal oscillator or resonator, set this bit to 1 . for a 12mhz crystal oscillator or resonator, clear this bit to 0 . note: isochronous endpoint 2 and endpoint 3 are implemented by hardware, so fifo2 and fifo3 cannot read/write via firmware. ucc (22h) register the awr register contains the current address and a remote wake up function control bit. the initial value of awr is 00h . the address value extracted from the the usb command has not to be loaded into this register until the setup stage has finished. bit no. label r/w power-on functions 0 wken r/w 0 usb remote-wake-up enable/disable (1/0) 1~7 ad0~ad6 r/w 0000000 usb device address awr (23h) register the stall register shows if the corresponding endpoint works properly or not. as soon as the endpoint works improp - erly, the related bit in the stall has to be set to 1 . the stall register will be cleared by a usb reset signal. bit no. label r/w power-on functions 0~4 stl0~stl4 r/w 00000 set by the user when related usb endpoints were stalled. cleared by a usb reset and a setup token event. 5~7 stl5~stl7 000 undefined bit, read as 0 . stall (24h) register
HT82A834R rev. 1.00 21 august 27, 2007 bit no. label r/w power-on functions 0 aset r/w 0 this bit is used to configure the sie to automatically change the device address by the value stored in the awr register. when this bit is set to 1 by firmware, the sie will update the device address by the value stored in the awr register after the pc host has successfully read the data from the device by an in operation. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the awr register. so, in order to work properly, the firmware has to clear this bit after a next valid setup token is received. 1 err r/w 0 this bit is used to indicate that some errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by firmware. this bit is used for all endpoint. 2 out r/w 0 this bit is used to indicate the out token (except the out zero length token) has been received. the firmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received. 3inr0 this bit is used to indicate the current usb receiving signal from pc host is an in token. 4 nak r 0 this bit is used to indicate the sie is a transmitted nak signal to the host in response to the pc host in or out token. 5 crcf r/w 0 error condition failure flag include crc, pid, no integrate token error, crcf will be set by hardware and the crcf need to be cleared by firmware. 6 eot r 1 token package active flag, low active. 7 nmi r/w 0 nak token interrupt mask flag. if this bit set, when the device sent a nak token to the host, an interrupt will be disabled. otherwise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt sub-routine. sies (25h) register the misc register combines command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. misc will be cleared by a usb reset signal. bit no. label r/w power-on functions 0 request r/w 0 after setting the status of the desired one, fifo can be requested by setting this bit high . after finishing, this bit must be set low. 1 tx r/w 0 to represent the direction and transition end mcu access. when set to logic 1, the mcu desires to write data to the fifo. after finishing, this bit must be set to logic 0 before terminating request to represent transition end. for an mcu read operation, this bit must be set to logic 0 and set to logic 1 after finishing. 2 clear r/w 0 mcu requests to clear the fifo, even if the fifo is not ready. after clearing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data. 3 iso_in_en r/w 0 enables the isochronous in pipe interrupt. 4 iso_out_en r/w 0 enables the isochronous out pipe interrupt. 5 setcmd r/w 0 to show that the data in the fifo is a setup command. this bit will remain in this state until the next one enters the fifo. 6 ready r 0 to show that the desired fifo is ready 7 len0 r 0 to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. misc (26h) register
HT82A834R rev. 1.00 22 august 27, 2007 bit no. label r/w power-on functions 0~1, 6~7 r0 undefined bit, read as 0 2 se0 r/w 0 this bit is used to indicate the sie has detected a se0 noise in the usb bus. this bit is set by sie and cleared by firmware. 3 se1 r/w 0 this bit is used to indicate the sie has detected a se1 noise in the usb bus. this bit is set by sie and cleared by firmware. 4 usbdn r 0 usbd- input 5 usbdp r 0 usbd+ input usb_state (1dh) register bit no. label r/w power-on functions 0 datatg* r/w 0 data token toggle bit 1 setio1** r/w 1 set endpoint1 input or output pipe (1/0), default input pipe(1) 2 setio2** r/w 0 set endpoint2 input or output pipe (1/0), default output pipe(0) 3 setio3** r/w 1 set endpoint3 input or output pipe (1/0), default input pipe(1) 4 setio4** r/w 1 set endpoint4 input or output pipe (1/0), default input pipe(1) 5~7 undefined bit, read as 0 note: *usb definition: when the host sends a set configuration , the data pipe should send the data0 (about the data toggle) first. so, when the device receives a set configuration setup command, the user needs to toggle this bit as the following data will send a data0 first. **it is only required to set the data pipe as an input pile or output pile. the purpose of this function is to avoid the host sending a abnormal in or out token and disabling the endpoint. setio (27h) register, usb endpoin t 1 ~ endpoint 4 set in/out pipe register the speaker output volume and speaker mute/un-mute are controlled by the usb speaker volume control register. the range of the volume is set from 6 db to -32 db by software. speaker mute control: muteb=0: mute speaker output (dac and pa will be mute) muteb=1: normal bit no. label r/w power-on functions 0~6 usvc0~ usvc6 r/w 0 volume control bit0~bit6 7 mute r/w 0 mute control, low active. usb speaker volume control (1ch) register
HT82A834R rev. 1.00 23 august 27, 2007 result (db) usvc result (db) usvc result (db) usvc result (db) usvc 6 000_1100 2 111_1100 10 110_1100 24 101_1100 5.5 000_1011 2.5 111_1011 10.5 110_1011 25 101_1011 5 000_1010 3 111_1010 11 110_1010 26 101_1010 4.5 000_1001 3.5 111_1001 11.5 110_1001 27 101_1001 4 000_1000 4 111_1000 12 110_1000 28 101_1000 3.5 000_0111 4.5 111_0111 13 110_0111 29 101_0111 3 000_0110 5 111_0110 14 110_0110 30 101_0110 2.5 000_0101 5.5 111_0101 15 110_0101 31 101_0101 2 000_0100 6 111_0100 16 110_0100 32 101_0100 1.5 000_0011 6.5 111_0011 17 110_0011 1 000_0010 7 111_0010 18 110_0010 0.5 000_0001 7.5 111_0001 19 110_0001 0 000_0000 8 111_0000 20 110_0000 0.5 111_1111 8.5 110_1111 21 101_1111 1 111_1110 9 110_1110 22 101_1110 1.5 111_1101 9.5 110_1101 23 101_1101 speaker volume control table label r/w power-on functions fifo0~ fifo4 r/w xxh epi accessing register (i = 0~4). when an endpoint is disabled, the corresponding accessing register should be disabled. fifo0~4 (28h~2ch) usb endpoint accessing register definitions dac_limit_l and dac_limit_h are used to define the 16-bit dac output limit. dac_limit_l and dac_limit_h are un- signed value. if the 16-bit data from the host over the range defined by dac_limit_l and dac_limit_h, the output digi- tal code to dac will be clamped. dac_limit_l dac output limit low byte dac_limit_h dac output limit high byte example to set the dac output limit value: ;----------------------------------------------------------- ; set dac limit value=ff00h ;----------------------------------------------------------- clr [02dh] ; set dac limit low byte=00h set [02eh] ; set dac limit high byte=ffh ;----------------------------------------------------------- in order to prevent a popping noise from the speaker output, the power amplifier should output a value of vdd/2 (send 8000h to dac) during the initial power on state. if the software is set high then clear the bit dac_wr_trig (bit 3 of dac_wr register), the value on the dac_limit_l and dac_limit_h registers will write to the dac. bit no. label r/w power-on functions 0 rec_mode r/w 0 the bit will determine the record source. rec_mode= 1 : record data comes from the record_in_h and record_in_l registers. rec_mode= 0 : record data comes from the pcm adc (default=0) 1~2, 4~7 r0 undefined bit, read as 0 . 3 dac_wr_trig r/w 0 dac write trigger bit dac_wr (2fh) register
HT82A834R rev. 1.00 24 august 27, 2007 note: rec_mode=1: writing to record_in_l register will only put the written data to an internal lower-order byte buffer (8-bit) and writing record_in_h will transfer the record_in_l and record_in_h registers con - tent to isochronous in buffer. when record interrupt happened, firmware should write 16-bit 2's complement value to record_in_l and record_in_h registers. example to avoid popping noise: system_initial: ;----------------------------------------------------------- ; avoid pop noise ;----------------------------------------------------------- mov a,wdts mov fifo_temp,a ;save wdts value mov a,00001111b andm a,wdts mov a,01010000b orm a,wdts ;enter dac write data mode, high nibble of wdts=0101b clr [02dh] ;set dac data low byte=00h mov a,80h mov [02eh],a ;set dac data high byte=80h nop ;write 8000h to dac set [02fh].3 nop clr [02fh].3 nop ;----------------------------------------------------------- mov a,fifo_temp ;restore wdts value mov wdts,a ;quit dac write data mode ;----------------------------------------------------------- note: at dac write data mode (high nibble of wdts register is 0101b), dac_limit_l and dac_limit_h registers will be the 16-bit dac input data register at falling edge of dac_wr_trig. otherwise, these two registers are used to define the 16-bit dac output limit. digital pga bit no. label functions 0~5 pga0~pga5 there are six bits to control the digital pga (0~19.5 db). the pga is a digital amplifier used to amplify the 16-bit data that comes from the pcm adc (rec_mode(2fh.0=0)=0) or from the record_in_h and record_in_l (rec_mode(2fh.0)=1). the pga value versus gain relationship is shown in the follow table. 6 adc_reset adc_reset= 1: pcm adc at reset condition adc_reset= 0: pcm adc during normal operation (default=0) the following conditions will reset the adc: mcu reset or usb reset set adc_reset to 1 7 mute_mkb microphone mute control: mute_mkb= 0: mute microphone input. mute_mkb= 1: normal. pga_ctrl (30h) register
HT82A834R rev. 1.00 25 august 27, 2007 pga_crtl value (pga5~pga0) gain (db) 000000 0 000001 0.5 : : : : 100111 19.5 101000 19.5 : : : : 111111 19.5 pfd control label bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pfdc 0 pres1 pres0 pfden 0 0 pfd_io selw pfdd pfdd7 pfdd6 pfdd5 pfdd4 pfdd3 pfdd2 pfdd1 pfdd0 the pfd (programmable frequency divider) is implemented in the HT82A834R. it is composed of two portions: a prescaler and a general counter. the prescaler is controlled by the register bits, pres0 and pres1. the 4-stage prescaler is divided by 16. the general counter is programmed by an 8-bit register pfdd. the pfdd is inhibited to write while the pfd is disabled. to modify the pfdd contents, the pfd must be enabled. when the generator is disabled, the pfdd is cleared by hardware. pfd prescaler selection: pres1 pres0 prescaler output 00 pfd frequency source 1 01 pfd frequency source 2 10 pfd frequency source 4 11 pfd frequency source 8 the bit pfd_io is used to determine whether pc0 is a general purpose i/o port or a pfd output. label functions pfd_io=1 pc0 is pfd output pfd_io=0 pc0 is a general purpose io port (default =0) the selw bit is used to control the power amplifier input source. the software should set selw= 1 when the power amplifier signal come from music_in, otherwise the speaker output will come from usb audio data. label functions selw=1 power amplifier signal is sourced from music_in pin selw=0 power amplifier signal is sourced from usb audio data (default =0) # / ( 0 0 9 % & 4 ( 8 6 . . h & ' 5 % ' ) & . . . '
d % . % % . h % i 5 % ; " % % i % " % = & %
# % " % . % & % 1 % % 4 > 6
HT82A834R rev. 1.00 26 august 27, 2007 spi the serial interface function similar to spi (motorola), where four basic signals are included. they are sdi (serial data input), sdo (serial data output), sck (serial clock) and scs (slave select pin). label functions d7 d6 d5 d4 d3 d2 d1 d0 sbcr serial bus control register cks m1 m0 sben mls csen wcol trf default 01100000 sbdr serial bus data register d7 d6 d5 d4 d3 d2 d1 d0 default uuuuuuuu note: u unchanged two registers (sbcr & sbdr) unique to the serial interface provide control, status and data storage. sbcr: serial bus control register
bit7 (cks): clock source selection: f sio =f sys /2, select as 0; f sio =f sys , select as 1
bit6 (m1), bit5 (m0): master/slave mode and baud rate selection m1, m0= 00: master mode, baud rate = f sio 01: master mode, baud rate = f sio /4 10: master mode, baud rate = f sio /16 11: slave mode
bit4 (sben): serial bus enable/disable (1/0) enable: (scs dependent on csen bit) disable enable: sck, sdi, sdo, scs =0 (sck = 0 ) and wait to write data to sbdr (txrx buffer) master mode: write data to sbdr (txrx buffer) start transmission/reception automatically master mode: when data has been transferred set trf slave mode: when a sck (and scs dependent on csen) is received, data in txrx buffer is shifted-out and data on sdi is shifted-in. disable: sck (sck ), sdi, sdo, scs floating and related pins are io ports. label functions sben=1 pc4~pc7 are spi function pins (pin scs will go low if csen=1). sben=0 pc4~pc7 are general purpose i/o port pins (default) note: 1. if sben= 1 , the pull-high resistors on pc4~pc7 will be disabled. when this happens the user should add external pull-high resistors to the spi related pins if necessary (ex: pin scs ). 2. if csen= 0 , the scs pin will enter a floating state.
bit3 (mls): msb or lsb (1/0) shift first control bit
bit2 (csen): serial bus selection signal enable/disable (scs ), when csen=0, scs is floating
bit1 (wcol): this bit is set to 1 if data is written to sbdr (txrx buffer) when a data is transferring writing will be ignored if data is written to sbdr (txrx buffer) when a data is transferring wcol will be set by hardware and clear by software.
bit 0 (trf): data transferred or data received used to generate interrupt note: data receiving is still working when mcu enters halt mode + ( ) 8 ( ( 1 0 ( 3 3 ( 0 1 ( ( 8 ) ( + + ( ) 8 ( ( 1 0 ( 3 3 ( 0 1 ( ( 8 ) ( + spi timing
HT82A834R rev. 1.00 27 august 27, 2007 sbdr: serial bus data register data written to sbdr write data to txrx buffer only data read from sbdr read from sbdr only
operating mode description: master transmitter: clock sending and data i/o started by writing sbdr master clock sending started by writing sbdr slave transmitter: data i/o started by clock received slave receiver: data i/o started by clock received clock polarity = rising (clk ) or falling (clk): 1 or 0 (software option) operation of serial interface: label functions master select cks and select m1,m0 = 00, 01, 10 select csen, mls (same as slave) set sben writing data to sbdr data is stored in txrx buffer output clk (and scs ) signals go to step 5 (sio internal operation data stored in txrx buffer, and sdi data is shifted into txrx buffer data transferred, data in txrx buffer is latched into sbdr) check wcol; wcol = 1 clear wcol and go to step 4; wcol = 0 go to step 6 check trf or waiting for sbi (serial bus interrupt) read data from sbdr clear trf go to step 4 slave cks don t care and select m1, m0 = 11 select csen, mls (same as master) set sben writing data to sbdr data is store in txrx buffer waiting for master clock signal (and scs ): clk go to step 5 (sio internal operations clk (scs ) received output data in txrx buffer and sdi data is shifted into txrx buffer data transferred, data in txrx buffer is latched into sbdr) check wcol; wcol = 1 clear wcol, go to step 4; wcol = 0 go to step 6 check trf or waiting for sbi (serial bus interrupt) read data from sbdr clear trf go to step 4 wcol: master/slave mode, set if writing to sbdr when data is transferring (transmitting or receiving) and this writing will be ignored. wcol function can be enabled/disabled by software option (sio_wcol bit of mode_ctrl regis - ter). wcol is set by sio and cleared by users. data transmission and reception are still workable when mcu enters halt mode. cpol is used to select the clock polarity of clk. it is a software option (sio_cpol bit of mode_ctrl register). mls: msb or lsb first selection csen: chip select function enable/disable, csen = 1 scs signal function is active. master should output scs sig - nal before clk signal is setting and slave data transferring should be disabled(enabled) before(after) scs signal re - ceived. csen = 0, scs signal is not needed, scs pin (master and slave) should be floating. csen: csen software option (sio_csen bit of mode_ctrl register) is used to enable/disable software csen function. if csen software option is disable, software csen always disabled. if csen software option is enabled, software csen function can be used. sben = 1 serial bus standby; scs (csen = 1) = 1; scs = floating (csen = 0); sdi = floating; sdo = 1; master clk = output 1/0 (dependent on cpol software option), slave clk = floating sben = 0 serial bus disable; scs = sdi = sdo = clk = floating trf is set by sio and cleared by users. when data transferring (transmission and reception) is complete, trf is set to generate sbi (serial bus interrupt).
HT82A834R rev. 1.00 28 august 27, 2007 label functions d7 d6 d5 d4 d3 d2 d1 d0 sbcr serial bus control register cks m1 m0 sben mls csen wcol trf default 01100000 sbdr serial bus data register d7 d6 d5 d4 d3 d2 d1 d0 default uuuuuuuu + ( ) 8 ( ( 1 0 ( 3 3 ( 0 1 ( ( 8 ) ( + + ( ) 8 ( ( 1 0 ( 3 3 ( 0 1 ( ( 8 ) ( + ! ! , ' i 5 % ' i % % ; % %
% , % 4 # % & & 9 " " 6 sio timing , % 4 = % % 6 + 8 0 3 1 ) % , ! % , # # , ' 5 % ' 5 % %
& = & % , % &
b &
b
& ) 1 & % , % . & 5 % , ' ' %
% & = ' , ' , ' % , % , % ' : & ( : & . % , ! % . & block diagram of sio
HT82A834R rev. 1.00 29 august 27, 2007 label functions wcol set by sio cleared by users cesn enable or disable chip selection function pin master mode: 1/0=with/without scs output control slave mode: 1/0= with/without scs input control sben enable or disable serial bus (0= initialize all status flags) when sben=0, all status flags should be initialized when sben=0, all sio related function pins should stay at floating state trf 1= data transmitted or received 0= data is transmitting or still not received if clock polarity set to rising edge (sio_cpol=1), serial clock timing follow clk , otherwise (sio_cpol=0) clk is the serial clock timing. mode control the mode_ctrl register is used to control dac and adc operation mode and spi function. bit no. label functions 0 da_l_enb dac enable/disable control (left channel) 1= dac left channel disable 0= dac left channel enable (default) 1 da_r_enb dac enable/disable control (right channel) 1= dac right channel disable 0= dac right channel enable (default) 2 ad_enb adc enable/disable control 1= adc power down 0= adc power on (default) 3 play_mode dac play mode control 1= 8khz/16-bit 0= 48khz/16-bit (default) 4 sio_cpol there are three bits used to control the mode of spi operation. 1= clock polarity rising edge 0= clock polarity falling edge (default) 5 sio_wcol 1= wcol bit of sbcr register enable 0= wcol bit of sbcr register disable (default) 6 sio_csen 1= csen bit of sbcr register enable 0= csen bit of sbcr register disable (default) 7 record_freq 1= record frequency is 16khz 0= record frequency is 8 khz (default) mode_ctrl (34h) register spi usage example spi_test: clr ucc.@ucc_sysclk ;12mhz sysclk set sio_csen ;spi chip select function enable clr sio_cpol ;falling edge change data ;master mode, sclk=fsio clr m1 clr m0 ;-------------- clr cks ;fsio=fsys/2 clr trf ;clear trf flag clr trf_int ;clear interrupt spi flag set mls ;msb shift first set csen ;chip select enable set sben ;spi enable, scs will go low
HT82A834R rev. 1.00 30 august 27, 2007 if polling_mode clr esii ;spi interrupt disable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf jmp $0 clr trf else set esii ;spi interrupt enable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf_int ;set at spi interrupt jmp $0 clr trf_int endif play/record data the play/record interrupt will be activated when play/record data is valid on play_data/ record_data registers. the play_data/record_data registers will latch data until next interrupt happen. the play_data is unsigned value (0~ffffh). record_data is 2 s complement value (8000h~7fffh). the update rate of record_data is 8khz (record_freq=0) or 16khz (record_freq=1). the update rate of play_data is 48khz (play_mode=0) or 8khz (play_mode=1). all these registers (3ah~3fh) are read only. address label bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ah play_datal_l pl_d7 pl_d6 pl_d5 pl_d4 pl_d3 pl_d2 pl_d1 pl_d0 3bh play_datal_h pl_d15 pl_d14 pl_d13 pl_d12 pl_d11 pl_d10 pl_d9 pl_d8 3ch play_datar_l pr_d7 pr_d6 pr_d5 pr_d4 pr_d3 pr_d2 pr_d1 pr_d0 3dh play_datar_h pr_d15 pr_d14 pr_d13 pr_d12 pr_d11 pr_d10 pr_d9 pr_d8 3eh record_data_l r_d7 r_d6 r_d5 r_d4 r_d3 r_d2 r_d1 r_d0 3fh record_data_h r_d15 r_d14 r_d13 r_d12 r_d11 r_d10 r_d9 r_d8 configuration options the following table shows all of the configuration options in the microcontroller. all of the otp options must be defined to ensure proper system functioning. no. option 1 pa0~pa7 pull-high resistor enabled or disabled (by bit) 2 lvr enable or disable 3 wdt enable or disable 4 wdt clock source: f sys /4 or wdtosc 5 clrwdt instruction(s): 1 or 2 6 pa0~pa7 wake-up enabled or disabled (by bit) 7 pb0~pb7 pull-high resistor enabled or disabled (by bit) 8 pc0~pc7 pull-high resistor enabled or disabled (by nibble) 9 tbhp enable or disable (default disable)
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HT82A834R rev. 1.00 32 august 27, 2007 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82A834R rev. 1.00 33 august 27, 2007 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82A834R rev. 1.00 34 august 27, 2007 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82A834R rev. 1.00 35 august 27, 2007
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82A834R rev. 1.00 36 august 27, 2007
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82A834R rev. 1.00 37 august 27, 2007
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82A834R rev. 1.00 38 august 27, 2007
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). if an in- terrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82A834R rev. 1.00 39 august 27, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82A834R rev. 1.00 40 august 27, 2007
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82A834R rev. 1.00 41 august 27, 2007
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82A834R rev. 1.00 42 august 27, 2007
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82A834R rev. 1.00 43 august 27, 2007
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82A834R rev. 1.00 44 august 27, 2007
package information 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 HT82A834R rev. 1.00 45 august 27, 2007 0 ? 1 1 0 , . k $ c '
48-pin lqfp (7 7) outline dimensions symbol dimensions in mm min. nom. max. a 8.9 9.1 b 6.9 7.1 c 8.9 9.1 d 6.9 7.1 e 0.5 f 0.2 g 1.35 1.45 h 1.6 i 0.1 j 0.45 0.75 k 0.1 0.2 0 7 HT82A834R rev. 1.00 46 august 27, 2007 3 8 1 3 + 1 0 3 1 0 ? , ' . $ c j
product tape and reel specifications reel dimensions ssop 48w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 100 0.1 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 HT82A834R rev. 1.00 47 august 27, 2007 , 1
carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32 0.3 p cavity pitch 16 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 12 0.1 b0 cavity width 16.2 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 HT82A834R rev. 1.00 48 august 27, 2007 ) ' . 1 , ) )
HT82A834R rev. 1.00 49 august 27, 2007 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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